Semiconductor materials, such as patterned polysilicon, are commonly used as electrodes in integrated circuits. Among the many types of structures categorized as "electrodes" are transistor gates and capacitor plates. It is well known in the art to deposit and pattern a layer of polysilicon and then oxidize the resulting polysilicon structures to grow a layer of silicon dioxide. The quality and thickness of silicon dioxide grown on polysilicon can play an important role in the reliability and performance of an integrated circuit device. Two particular types of devices where this type of silicon dioxide plays a critical role are dynamic random access memory (DRAM) cells and nonvolatile memory devices employing "floating" gates.
Among the types of nonvolatile memory devices are erasable programmable read only memories (EPROMs). Within the group of EPROMs are "flash" EPROMs and "conventional" EPROMs (referred to herein as EEPROMs). Unlike EEPROMs which use Fowler-Nordheim tunneling for programming and erasing a floating gate, flash EPROMs use hot-electron injection to program and Fowler-Nordheim tunneling for erase.
While many different types of flash EPROM cells exist in the prior art, the single transistor flash EPROM cell (1-T cell) has become more prevalent due to its greater packing density. A prior art 1-T cell is set forth in FIG. 1 and designated by the general reference character 10. The 1-T cell 10 includes a substrate 12 having a channel 14, a source diffusion 16, and a drain diffusion 18. A tunnel oxide 20 separates the substrate 12 from a gate stack 22. The gate stack 22 is composed of a floating gate 24 an intergate dielectric 26, and a control gate 28.
During programming, the source 16 is grounded, and a positive voltage is applied to the control gate 28 with respect to the drain 18. Electrons are injected into the floating gate resulting in an overall higher memory cell threshold voltage (V.sub.TM). During erase, a positive voltage is applied to the source 16 with respect to the control gate 28, and electrons tunnel from the floating gate 24 to the source 16.
The fabrication of 1-T cells begins with the growth or deposition of the tunnel oxide 20. A layer of polysilicon is deposited over the tunnel oxide 20 to form a floating gate layer. The conductivity of the floating gate layer can be increased by in-situ doping or ion implantation. The interpoly dielectric 26 is then created on top of the floating gate 24. As shown in FIG. 1, the interpoly dielectric 26 is typically a three layer dielectric of silicon dioxide, silicon nitride, and silicon dioxide. It is common to form the first layer by oxidizing the polysilicon floating gate layer. A control gate layer is formed by depositing a second layer of polysilicon over the interpoly dielectric, and doping it, if required. The three layers (floating gate, interpoly dielectric, and control gate) are then patterned to create a number of gate stacks 22. The polycrystalline structure of the polysilicon gates (24 and 28) are shown in exaggerated form in FIG. 1. The gate stack 22 is subject to a subsequent oxidation step to form oxide sidewalls. The remainder of the fabrication process continues using well know steps (the so called "back-end" of the process). The back-end can include a number of additional temperature cycles.
Despite the advantages of flash EPROM technology, a number of reliability issues exist in the prior art. In flash EPROM memory designs a number of cells share a common source node allowing for the simultaneous (flash) erase of the entire memory array or a portion thereof (also referred to as a "sector" or a "block"). One problem raised by this erase function is that of "over-erase". In the event a cell possesses an erase (tunneling) current greater than the other cells in the array (or sector), during a given erase operation the cell having the higher erase current will be over-erased while the other cells are properly erased. Over-erase results in unacceptably low V.sub.TM and can result in the cell functioning as a depletion mode device. An aspect of the over-erase mechanism for floating gates of polysilicon construction is discussed in IEEE Technical Digest IEDM 1994, pp. 847-850 in an article entitled "The Solution of Over-Erase Problem Controlling Poly-Si Grain Size--Modified Scaling Principles for FLASH Memory" by Muramatsu et al. The article demonstrates how "oxide valleys" can occur at grain boundaries, and as a result, larger grain floating gates present larger distributions in V.sub.TM.
A number of methods addressing the over-erase problem are set forth in Proceedings of the IEEE, Vol. 81, No. 5, May 1993 in an article entitled "Reliability Issued of Flash Memory Cells" by Aritome et al. The methods set forth in Aritome et al. have drawbacks however. The use of a series enhancement transistor adds to process complexity, and increases overall cell size. The various verify-erase methods can require additional circuits and can increase erase time substantially.
A second reliability issue discussed in Aritome et al. is that of data retention. After a cell has been programmed, various mechanisms, including oxide defects can lead to the electrons leaking from the floating gate. Leakage paths can occur through the interpoly dielectric to the control gate, or through the tunnel oxide to the substrate as well. Data retention failures cause low V.sub.TM in programmed cells. A severe enough data retention problem results in programmed cells having V.sub.Tm s that approach those of erased cells.
Commonly-owned, U.S. Pat. No. 5,416,738 entitled SINGLE TRANSISTOR FLASH EPROM CELL AND METHOD OF OPERATION, incorporated by reference herein, discloses a flash EPROM arrangement wherein a negative voltage is applied to non-selected cells during read operations to tolerate a wider range of erased (and even over-erased) cell V.sub.TM s.
While the interpoly dielectric of flash EPROM cells can play an important role in the reliability of the flash devices, a similar structure also plays an important part in DRAM cells. It is known in the prior art to fabricate DRAM cells having a cell capacitor formed by a sandwich layer of a first layer of polysilicon, a capacitor dielectric and a second layer of polysilicon. To increase the sensed DRAM cell signal, various methods have been introduced to increase the capacitance of the cell capacitor. Such approaches have addressed three variables of cell design; increasing capacitor area, using dielectrics having higher dielectric constants, and reducing the dielectric thickness. For example, it is known to increase capacitor area by depositing a "textured" layers of polysilicon. To increase dielectric permittivity it is known to use higher dielectic constant materials such as oxy-nitride or tantalum oxide. Reducing the dielectric thickness requires attention to properties such as the polysilicon interface and grain size which change as a function of growth and back-end temperature cycles. The grain structure affects the quality of the dielectric (such as its leakage properties, as described above).
In a field unrelated to floating gate technology, an improved local oxidation of silicon (LOCOS) technique is presented that utilizes nitrogen-doped amorphous silicon to reduce the stress and formation of voids during LOCOS in IEEE Technical Digest IEDM 1994, pp. 683-686 in an article entitled "Nitrogen in-situ doped Poly Buffered LOCOS: Simple and Scalable Isolation Technology for Deep Submicron Silicon Devices" by Kobayashi et al.
While those references directed to flash EPROMs provide many solutions to the over-erase problem, arrays of 1-T flash cells continue to be manufactured with V.sub.TM distributions that are either too wide to compensate for with the prior art methods, or, if correctable by prior art methods, would introduce additional process complexity or an unacceptable amount of additional circuitry. It is therefore desirable to provide an EPROM cell design that results in tighter V.sub.TM distributions without increasing process complexity. Further, it is always desirable to provide a DRAM cell with a capacitor having increased capacitance and a dielectric of increased reliability.